The present disclosure relates to a semiconductor integrated circuit device provided with an SRAM (static random access memory) cell including a transistor with a fin structure.
The increasing miniaturization of LSIs has lead to significant changes in transistor structures. Specifically, instead of planar-type transistors which have been a major trend in the past, recently, transistors with a three-dimensional (3D) structure have increasingly come to be used. A representative example of a 3D transistor is a transistor with a fin structure (hereinafter referred to as a fin-type transistor).
FIG. 7 schematically illustrates an outline of a fin-type transistor. Unlike a MOS transistor with its two-dimensional structure, a fin-type transistor has a source and a drain with a three-dimensional structure that rises up vertically and is referred to as a fin. Moreover, the fin-type transistor has a gate which is arranged so as to wrap around the fin. In this fin structure, a channel region is defined by three surfaces of the fin. This leads to a significantly improved channel controllability as compared to conventional structures. As a result, various advantages, including reduced leakage power, increased ON-state current, and lowered operating voltage, are achieved. This improves the performance of semiconductor integrated circuits.
One type of memory circuits employed in LSIs are SRAM (static random access memory) circuits. A structure of an SRAM cell using a fin-type transistor is disclosed in United States Patent No. 2013/0258759.